With the development of technology, non-volatile memory such as flash memory has been widely applied in various electronic products. For example, NAND flash-based solid-state disks (SSDs) are promising nowadays. Compared with traditional hard disk drives (HDDs), SSDs have advantages in small form factor, low power, and superior random read performance.
One main challenge in design flash memory is dealing with the bit error rate (BER). Flash memory is prone to bit errors, and the BER increases with more programming and erasing cycles. In such case, the memory controller needs to spend more time performing error detection and correction on the inputted data, and the decoding speed is reduced.
Therefore, there is a need for a storage device capable of speeding up the ECC decoding process of memory and an operating method thereof.